This invention relates to electronic testers for integrated circuit chips; and more particularly, it relates to electronic testers which send multiple test vectors to a chip and determine whether any such test vector causes a current I.sub.ddq to flow through the chip above a predetermined test limit.
Many present-day integrated circuit chips contain over 1 million transistors. And, when a chip is made, any one of the transistors on the chip can contain a defect. Thus, each integrated circuit chip is usually tested by an electronic tester before the chip is permanently soldered into another type of assembly, such as a multi-chip module.
In the prior art, one test which is made in order to find a defective transistor on an integrated circuit chip is called an I.sub.ddq test. This test is performed, for example, by an electronic tester called the Schlumberger ITS 9000, which costs about five million dollars.
To perform the I.sub.ddq test in the prior art, a chip is connected through a first electromechanical relay to a large power supply which has a large current capacity. Then, a test vector is sent to the chip. Thereafter, the chip is connected through a second electromechanical relay to a small power supply which has a small current capacity, and the first relay to the large power supply is opened. Then, the current I.sub.ddq to the chip from the small power supply is measured with a high degree of accuracy.
If the current I.sub.ddq is less than a predetermined test limit, the large power supply is again connected to the chip via the first relay and the small power supply is disconnected from the chip via the second relay. Then another test vector is sent to the chip, and the sequence continues as described above. On the other hand, if the measured current I.sub.ddq exceeds the predetermined test limit, then the test is terminated, and the chip is identified as being defective.
One problem, however, with the above-described test, it that it can actually cause a chip to fail when the chip itself does not otherwise contain any defective transistors. This can occur as follows.
Ideally, each test vector which is sent to the chip should contain no errors. However, in order to test all of the transistors on an entire chip, about three million test vectors usually need to be sent to the chip. Consequently, when the test vectors are initially generated, some of them may contain an error.
When an erroneous test vector is sent to the chip, it can cause a power bus in the chip to be shorted through various transistors in the chip to ground. If that occurs, the current capacity of the small power supply will be exceeded; and as a result, the voltage from the small power supply will drop towards to ground. At the same time, however, the erroneous test vector with its full voltage levels will continue to be applied by the tester to the chip. Consequently, some transistors on the chip will receive input voltages from the test vector which exceed the chip's power bus voltage; and that can destroy the transistor's operating characteristics.
Also, as the voltage from the small power supply drops towards ground, the set/reset state of any flip-flops on the chip will dissipate. Consequently, even if no transistors on the chip are destroyed by the erroneous test vector, the test cannot proceed by sending the next sequential test vector to the chip. That is because the output signals which come from the chip depend upon both the test vector which the chip receives and the set/reset states of the chip's internal flip-flops.
Accordingly, a primary object of the present invention is to provide a tester for integrated circuit chips in which the above drawbacks are overcome.